In references [1-3], methods of implementing high-reverse-voltage MOST by utilizing optimum surface variation lateral doping are provided. Using such methods, a lateral interdigitated semiconductor device is formed in a surface of a lightly doped substrate of a first semiconductor type, wherein it comprises at least one device which includes a region having the same potential with the substrate and a region with its voltage variable from zero to the largest reverse bias taking substrate as reference; it can also comprises other device(s) device, including a region having a voltage variable from zero to the largest reverse bias and a region with its voltage being the largest reverse bias taking substrate as reference. In the present invention, the surface region from the floating voltage region to the region in contact with the substrate is defined as a first surface voltage sustaining region, and the surface region from the largest reverse bias region to the floating voltage region is defined as a second surface voltage sustaining region. The two voltage sustaining regions are formed by superposition of thin layer(s) of a first conductivity type and thin layer(s) of a second conductivity type alternatively, wherein the thin layer contacted directly to the substrate is of a second conductivity type. Said thin layer of a second conductivity type contacted directly to the substrate is directly connected to the largest voltage portion in the voltage sustaining region and other thin semiconductor layers of a second conductivity type are connected to the largest voltage region via a region close to it, or are connected to it at the finger end of interdigitated layout. Each of the regions of a first conductivity type is connected to the smallest voltage region via a region close to it, or it is connected to the region at the finger end of interdigitated layout. When the first conductivity type is p-type, the largest voltage is positive. When the first conductivity type is n-type, the largest voltage is negative. Said total thickness of all thin layers should be less than the thickness of the depletion layer of a one-sided abrupt plane junction of the same substrate under the largest reverse bias. The amount of effectively ionized impurity per area of a second conductivity type in the thin layer of a second conductivity type contacted directly to the substrate in each surface voltage sustaining region can varies with distance, but should be not more is than 2D0, where D0 is the impurity density of a second conductivity type in the depletion region of the heavily-doped side of a one-sided abrupt parallel-plane junction formed by the same substrate under the largest reverse bias. Besides, for the second surface voltage sustaining region, the impurity density of the thin layer of a second conductivity type in contact with substrate should be not less than D0. In addition, the impurity density of the portion close to the largest voltage region in each layer of each voltage sustaining region should be not more than 2D0 and the impurity density of the region close to the lowest voltage region should be not more than 1.8D0.
Between the two surface voltage-sustaining regions, there is a carrier isolation region having the surface dimension much less than those of the two surface voltage sustaining regions.
The key point of optimum surface variation lateral doping technology is that, that the overall effective impurity of second conductivity type decreases gradually or stepwisely with the increase of the distance from the portion having the largest voltage in the voltage sustaining region, and approaches zero in the lowest voltage region. Where the overall effective impurity density of second conductivity type is defined as the value of the sum of the effective impurity density of all layers of a second conductivity type in a surface area subtracts the sum of the effective impurity density of all layers of first conductivity type in the same surface area, and then divided by the area. Wherein the surface area has dimensions in any direction being much smaller than the thickness of the depletion region of a one-sided abrupt parallel-plane junction made by the same substrate under the largest reverse bias.
Based on Ref. [2 and 3], many power integrated circuits can be realized. FIG. 1 shows an application where the load is a fluorescent lamp. The switches of SH and SL and their drivers can all be realized according to Ref. [2 and 3]. In this figure, V is the voltage of the external power supply. When SH is switched on, the current flows from the positive terminal V, via SH, capacitor C, the load, the inductance L, and finally reaches the negative terminal of the power supply illustrated as “−” in the figure. When SH is switched off, since the current through the inductance should be continuous, the C is being charged via the diode D1. After a short duration, SL is switched on, then the capacitor C is discharged via SL, L and the load. In the next stage that SL is switched off, the current flows from terminal “−”, via L, the load, C, D2 and finally reaches terminal “+V”. It should be noted that diodes D1 and D2 must be high-voltage fast recover diode or high voltage Schottky diodes. So, if SH and SL are realized by using the method in [2 and 3], the two diodes must be connected externally, leading to a higher packaging cost at least.